The present invention relates to integrated circuit (chip) design, and more specifically, to synthesis of a logical chip design to a physical design.
Computer-aided design (CAD) tools aid in the design of circuits that will ultimately be implemented as semiconductor devices. The process of converting the logical (circuit) design to the physical realization of the design is referred to as synthesis and generally results in a gate-level placed netlist (list of connections). The implementation can be organized as a set of blocks, each with a set of components. Each sub-block has a primary input and primary output for power that is then divided within the sub-block. Synthesis of a logical design typically includes input of objective functions that direct the synthesis engine to achieve a particular design. The objective functions may specify timing constrains and a power budget, for example. The timing constraints may be provided with enough specificity to ensure that the chip performance is within design tolerances. That is, as opposed to an overall budget, timing constraints may be specified on the pin level. In the physical design resulting from the synthesis, these constraints may be manifested in the length of wires and placement of devices, for example.